#include"VIEU.h"

inline int VIEU::get_delay() {
    return this->delay_cycles;
}

void VIEU::input_operands(std::vector<base_operand*>* operands){
    this->operand_list = operands;
}
inline uint64_t VIEU::read_Reg(int reg_id) {
    return this->RF->get_vec_register_value(reg_id)->at(this->id);
}


inline void VIEU::write_Reg(int reg_id, uint64_t value, int delay) {
    // return set_vec_regsiter_single(reg_id, this->id, value);
    this->res_value = value;
    this->dst_reg_id = reg_id;
    this->delay_cycles = delay;
}

write_req_info_reg  VIEU::upload_write_msg() {
    write_req_info_reg res;
    res.value = this->res_value;
    res.reg_id = this->dst_reg_id;
    res.delay = this->delay_cycles;
    return res;
}

int64_t sign_extend_24_to_64(int32_t imm24) {
    int32_t masked = imm24 & 0xFFFFFF;
    // 左移40位，然后算术右移40位，自动进行符号扩展
    return (static_cast<int64_t>(masked) << 40) >> 40;
}

//对src1为imm的情况进行处理，对6位的立即数进行符号扩展
inline int32_t imm_6_signed_inflation(uint64_t imm) {
    if (imm & 0x20) { //检查第6位（符号位）
        return static_cast<int32_t>(imm | 0xFFFFFFC0); //符号扩展为32位
    } else {
        return static_cast<int32_t>(imm & 0x3F); //保持原值
    }
}

inline int64_t imm_6_signed_inflation_64(uint64_t imm) {
    if (imm & 0x20) { //检查第6位（符号位）
        return static_cast<int64_t>(imm | 0xFFFFFFFFFFFFFFC0); //符号扩展为64位
    } else {
        return static_cast<int64_t>(imm & 0x3F); //保持原值
    }
}

inline uint64_t VIEU::do_VADD_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    //这里我们考虑控制寄存器的操作
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t bits_src1 = static_cast<int64_t>(src1);
    int64_t bits_src2 = static_cast<int64_t>(src2);

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_ADD;
    //VCR中AS标志位在第7位
    // 对吗???
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 > 0 && bits_src2 > 0 && bits_src1 + bits_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //上溢出
            //[61:60], [C1, MSB1] = 01
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD overflow exception");
            }
            
            res = 0x7FFFFFFFFFFFFFFF;
        }else if (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0){
            //下溢出
            //[61:60], [C1, MSB1] = 10
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD underflow exception");
            }
            res = 0x8000000000000000;
        }else{
            
            // uint64_t mask1 = ~ 1ULL;
            // vst &= mask1;
            
            res = static_cast<uint64_t>(bits_src1 + bits_src2);
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对VST控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VADD_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    int64_t bits_src1 = imm_6_signed_inflation_64(imm);
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t bits_src2 = static_cast<int64_t>(src2);

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_ADD;
    //VCR中AS标志位在第7位
    // 对吗???
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 > 0 && bits_src2 > 0 && bits_src1 + bits_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //上溢出
            //[61:60], [C1, MSB1] = 01
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD overflow exception");
            }
            
            res = 0x7FFFFFFFFFFFFFFF;
        }else if (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0){
            //下溢出
            //[61:60], [C1, MSB1] = 10
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD underflow exception");
            }
            res = 0x8000000000000000;
        }else{
            
            // uint64_t mask1 = ~ 1ULL;
            // vst &= mask1;
            
            res = static_cast<uint64_t>(bits_src1 + bits_src2);
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对VST控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VADDU_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t bits_src1 = read_Reg(src1_reg_id);
    uint64_t bits_src2 = read_Reg(src2_reg_id);
    

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 + bits_src2 < bits_src1 || bits_src1 + bits_src2 < bits_src2)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU overflow exception");
                res = bits_src1 + bits_src2;
            } else {
                res = 0xFFFFFFFFFFFFFFFF;
            }
        }else{
            res = bits_src1 + bits_src2;
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对VST控制寄存器的修改写回
    write_Reg(176, vst, 1);

    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VADDU_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t bits_src1 = imm;
    uint64_t bits_src2 = read_Reg(src2_reg_id);
    

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 + bits_src2 < bits_src1 || bits_src1 + bits_src2 < bits_src2)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU overflow exception");
                res = bits_src1 + bits_src2;
            } else {
                res = 0xFFFFFFFFFFFFFFFF;
            }
        }else{
            res = bits_src1 + bits_src2;
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对VST控制寄存器的修改写回
    write_Reg(176, vst, 1);

    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VADD32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    int32_t low_src1 = static_cast<int32_t>(src1 & 0xFFFFFFFF);
    int32_t high_src1 = static_cast<int32_t>((src1 >> 32) & 0xFFFFFFFF);
    int32_t low_src2 = static_cast<int32_t>(src2 & 0xFFFFFFFF);
    int32_t high_src2 = static_cast<int32_t>((src2 >> 32) & 0xFFFFFFFF);

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((low_src1 > 0 && low_src2 > 0 && low_src1 + low_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else if (low_src1 < 0 && low_src2 < 0 && low_src1 + low_src2 > 0){
            vst |= MASK_SIGN_UNDER_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x80000000;
            }
        }else{
            res_low = static_cast<uint64_t>(low_src1 + low_src2);
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }

    try {
        if ((high_src1 > 0 && high_src2 > 0 && high_src1 + high_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {
                res_high = 0x7FFFFFFF;
            }
        }else if (high_src1 < 0 && high_src2 < 0 && high_src1 + high_src2 > 0){
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {            
                res_high = 0x80000000;
            }
        }else{
            res_high = static_cast<uint64_t>(high_src1 + high_src2);
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    res = (res_high << 32) | (res_low);
    write_Reg(dst_reg_id, res, 1);
    return res;
}


inline uint64_t VIEU::do_VADD32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    int32_t src1 = imm_6_signed_inflation(imm);
    uint64_t src2 = read_Reg(src2_reg_id);

    int32_t low_src1 = static_cast<int32_t>(src1 & 0xFFFFFFFF);
    int32_t high_src1 = static_cast<int32_t>((src1 >> 32) & 0xFFFFFFFF);
    int32_t low_src2 = static_cast<int32_t>(src2 & 0xFFFFFFFF);
    int32_t high_src2 = static_cast<int32_t>((src2 >> 32) & 0xFFFFFFFF);

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((low_src1 > 0 && low_src2 > 0 && low_src1 + low_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else if (low_src1 < 0 && low_src2 < 0 && low_src1 + low_src2 > 0){
            vst |= MASK_SIGN_UNDER_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x80000000;
            }
        }else{
            res_low = static_cast<uint64_t>(low_src1 + low_src2);
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }

    try {
        if ((high_src1 > 0 && high_src2 > 0 && high_src1 + high_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {
                res_high = 0x7FFFFFFF;
            }
        }else if (high_src1 < 0 && high_src2 < 0 && high_src1 + high_src2 > 0){
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADD32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {            
                res_high = 0x80000000;
            }
        }else{
            res_high = static_cast<uint64_t>(high_src1 + high_src2);
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADD32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    res = (res_high << 32) | (res_low);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VADDU32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (low_src1 + low_src2 < low_src1 || low_src1 + low_src2 < low_src2){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_UNSIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else{
            res_low = low_src1 + low_src2;
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    try {
        if (high_src1 + high_src2 < high_src1 || high_src1 + high_src2 < high_src2){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {    
                res_high = 0xFFFFFFFF;
            }
        }else{
            res_high = high_src1 + high_src2;
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    res = (res_high << 32) | (res_low);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VADDU32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint32_t src1 = imm & 0xFFFFFFFF;
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_ADD;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (low_src1 + low_src2 < low_src1 || low_src1 + low_src2 < low_src2){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_UNSIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 + low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else{
            res_low = low_src1 + low_src2;
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    try {
        if (high_src1 + high_src2 < high_src1 || high_src1 + high_src2 < high_src2){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VADDU32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 + high_src2);
            } else {    
                res_high = 0xFFFFFFFF;
            }
        }else{
            res_high = high_src1 + high_src2;
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VADDU32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    res = (res_high << 32) | (res_low);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUB_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    int64_t bits_src1 = static_cast<int64_t>(src1);
    int64_t bits_src2 = static_cast<int64_t>(src2);
    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 > 0 && bits_src2 < 0 && bits_src1 - bits_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //上溢出
            //[61:60], [C1, MSB1] = 01
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB overflow exception");
                res = static_cast<uint64_t>(bits_src1 - bits_src2);
            } else {
                res = 0x7FFFFFFFFFFFFFFF;
            }
        }else if (bits_src1 < 0 && bits_src2 > 0 && bits_src1 - bits_src2 > 0){
            //下溢出
            //[61:60], [C1, MSB1] = 10
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB underflow exception");
                res = static_cast<uint64_t>(bits_src1 - bits_src2);
            } else {
                res = 0x8000000000000000;
            }
        }else{
            res = static_cast<uint64_t>(bits_src1 - bits_src2);
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对vst控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUB_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    int64_t bits_src1 = imm_6_signed_inflation_64(imm);
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t bits_src2 = static_cast<int64_t>(src2);

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((bits_src1 > 0 && bits_src2 < 0 && bits_src1 - bits_src2 < 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //上溢出
            //[61:60], [C1, MSB1] = 01
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB overflow exception");
                res = static_cast<uint64_t>(bits_src1 - bits_src2);
            } else {
                res = 0x7FFFFFFFFFFFFFFF;
            }
        }else if (bits_src1 < 0 && bits_src2 > 0 && bits_src1 - bits_src2 > 0){
            //下溢出
            //[61:60], [C1, MSB1] = 10
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB underflow exception");
                res = static_cast<uint64_t>(bits_src1 - bits_src2);
            } else {
                res = 0x8000000000000000;
            }
        }else{
            res = static_cast<uint64_t>(bits_src1 - bits_src2);
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对vst控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBU_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t u_src1 = read_Reg(src1_reg_id);
    uint64_t u_src2 = read_Reg(src2_reg_id);

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (u_src1 - u_src2 > u_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU overflow exception");
                res = u_src1 - u_src2;
            } else {
                res = 0x0000000000000000;
            }
        }else{
            res = u_src1 - u_src2;
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对vst控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBU_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t u_src1 = imm;
    uint64_t u_src2 = read_Reg(src2_reg_id);

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (u_src1 - u_src2 > u_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU overflow exception");
                res = u_src1 - u_src2;
            } else {
                res = 0x0000000000000000;
            }
        }else{
            res = u_src1 - u_src2;
        }
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    //将对vst控制寄存器的修改写回
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBC(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    int64_t bits_src1;
    std::memcpy(&bits_src1, &src1, sizeof(bits_src1));
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  
    if(bits_src2>=bits_src1){
        res = ((bits_src2-bits_src1) << 1) + 1;
    }
    else{
        res = bits_src2 << 1;
    }
    
    write_Reg(dst_reg_id, res, 1);
    return res;
}
    
inline uint64_t VIEU::do_VSUB32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    int64_t bits_src1;
    std::memcpy(&bits_src1, &src1, sizeof(bits_src1));
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  

    int64_t low_src1 = (bits_src1 ) & 0xFFFFFFFF;
    int64_t high_src1 = (bits_src1 >> 32) & 0xFFFFFFFF;
    int64_t low_src2 = (bits_src2 ) & 0xFFFFFFFF;
    int64_t high_src2 = (bits_src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    int64_t res_low;
    int64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((low_src1 < 0 && low_src2 > 0 && low_src1 - low_src2 > 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UNDER_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x80000000;
            }
        }else if (low_src1 > 0 && low_src2 < 0 && low_src1 - low_src2 < 0){
            vst |= MASK_SIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else{
            res_low = static_cast<uint64_t>(low_src1 - low_src2);
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }

    try {
        if ((high_src1 < 0 && high_src2 > 0 && high_src1 - high_src2 > 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {
                res_high = 0x80000000;
            }
        }else if (high_src1 > 0 && high_src2 < 0 && high_src1 - high_src2 < 0){
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {            
                res_high = 0x7FFFFFFF;
            }
        }else{
            res_high = static_cast<uint64_t>(high_src1 - high_src2);
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    int64_t res_64 = (res_high << 32) | (res_low);
    res = static_cast<uint64_t>(res_64);
    write_Reg(dst_reg_id, res, 1);
    return res;
}
   
inline uint64_t VIEU::do_VSUB32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);

    int64_t bits_src1 = static_cast<int64_t>(imm);
    int64_t bits_src2 = static_cast<int64_t>(src2);    

    int64_t low_src1 = (bits_src1 ) & 0xFFFFFFFF;
    int64_t high_src1 = (bits_src1 >> 32) & 0xFFFFFFFF;
    int64_t low_src2 = (bits_src2 ) & 0xFFFFFFFF;
    int64_t high_src2 = (bits_src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    int64_t res_low;
    int64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_SIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if ((low_src1 < 0 && low_src2 > 0 && low_src1 - low_src2 > 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UNDER_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x80000000;
            }
        }else if (low_src1 > 0 && low_src2 < 0 && low_src1 - low_src2 < 0){
            vst |= MASK_SIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 low overflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x7FFFFFFF;
            }
        }else{
            res_low = static_cast<uint64_t>(low_src1 - low_src2);
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }

    try {
        if ((high_src1 < 0 && high_src2 > 0 && high_src1 - high_src2 > 0)){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            vst |= MASK_SIGN_UNDER_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {
                res_high = 0x80000000;
            }
        }else if (high_src1 > 0 && high_src2 < 0 && high_src1 - high_src2 < 0){
            vst |= MASK_SIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUB32 high overflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {            
                res_high = 0x7FFFFFFF;
            }
        }else{
            res_high = static_cast<uint64_t>(high_src1 - high_src2);
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUB32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    int64_t res_64 = (res_high << 32) | (res_low);
    res = static_cast<uint64_t>(res_64);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBU32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint32_t low_src1 = (src1 ) & 0xFFFFFFFF;
    uint32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint32_t low_src2 = (src2 ) & 0xFFFFFFFF;
    uint32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (low_src1 - low_src2 > low_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x00000000;
            }
        }else{
            res_low = low_src1 - low_src2;
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    try {
        if (high_src1 - high_src2 > high_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {
                res_high = 0x00000000;
            }
        }else{
            res_high = high_src1 - high_src2;
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    int64_t res_64 = (res_high << 32) | (res_low);
    res = static_cast<uint64_t>(res_64);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBU32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id); 

    uint64_t low_src1 = (imm) & 0xFFFFFFFF;
    uint64_t high_src1 = (imm >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = (src2) & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res;
    uint64_t res_low;
    uint64_t res_high;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //先将SIGN位置1，有符号操作，加法操作OP为0，因此先置位1000...0000
    vst |= MASK_UNSIGN_SUB;
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (low_src1 - low_src2 > low_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW_LOW;
            vst |= MASK_SATa0;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU32 low underflow exception");
                res_low = static_cast<uint64_t>(low_src1 - low_src2);
            } else {
                res_low = 0x00000000;
            }
        }else{
            res_low = low_src1 - low_src2;
        }//低半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU32 Low 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    try {
        if (high_src1 - high_src2 > high_src1){//|| (bits_src1 < 0 && bits_src2 < 0 && bits_src1 + bits_src2 > 0)) {
            //溢出
            //[C1] = 1
            vst |= MASK_UNSIGN_UP_OVERFLOW;
            vst |= MASK_SATa1;
            if (!overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VSUBU32 high underflow exception");
                res_high = static_cast<uint64_t>(high_src1 - high_src2);
            } else {
                res_high = 0x00000000;
            }
        }else{
            res_high = high_src1 - high_src2;
        }//高半字饱和操作
    } catch (const std::overflow_error& e) {
        std::cerr << "Overflow error in VSUBU32 High 32 bits operation: " << e.what() << std::endl;
        //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
    }
    write_Reg(176, vst, 1);
    int64_t res_64 = (res_high << 32) | (res_low);
    res = static_cast<uint64_t>(res_64);
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSUBC32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res_low;
    uint64_t res_high; 

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    if(low_src2 >= low_src1){
        res_low = ((low_src2 - low_src1) << 1) + 1;
    }
    else{
        res_low = low_src2 << 1;
    }

    if(high_src2 >= high_src1){
        res_high = ((high_src2 - high_src1) << 1) + 1;
    }
    else{
        res_high = high_src2 << 1;
    }
    
    uint64_t res = (res_high << 32) | res_low;
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline double VIEU::do_VSAT(int src1_reg_id, int src2_reg_id, int dst_reg_id){} //op = 111_0101_000; execution cycle = 1;未写
    
inline double VIEU::do_VSAT32(int src1_reg_id, int src2_reg_id, int dst_reg_id){} //op = 101_0101_000; execution cycle = 1；未写

inline uint64_t VIEU::do_VNEG(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));
    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (bits_src2 == 0x8000000000000000){
            //溢出
            res = bits_src2;
            vst |= MASK_SATa0;
            if (overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VNEG overflow exception");
                }
            } else {res = 0 - bits_src2;}
        } catch (const std::overflow_error& e) {
            std::cerr << "Overflow error in VNEG operation: " << e.what() << std::endl;
            //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
            }
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VNEG32(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id); 

    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res_low;
    uint64_t res_high;
    uint64_t VST = read_Reg(176);//VST的enum值是176

    uint64_t res;
    bool overflow = false;
    uint64_t vst = read_Reg(176);//VST的enum值是176
    uint64_t vcr = read_Reg(181);//VCR的enum值是181
    //VCR中AS标志位在第7位
    if((vcr & (1 << 7)) == 0){
        overflow = true;
    }
    try {
        if (low_src2 == 0x80000000){
            //低32位溢出
            res_low = low_src2;
            vst |= MASK_SATa1;
            vst |= MASK_SATa0;
            if (overflow) {
                //非饱和运算则抛出异常
                throw std::overflow_error("VNEG32 overflow Low 32 bits exception");
                }
            } else if (high_src2 == 0x80000000){
                //高32位溢出
                res_high = high_src2;
                vst |= MASK_SATa1;
                vst |= MASK_SATa0;
                if (overflow) {
                    //非饱和运算则抛出异常
                    throw std::overflow_error("VNEG32 overflow High 32 bits exception");
                    }
                } else {
                    res_low = 0 - low_src2;
                    res_high = 0 - high_src2;
                    }
        } catch (const std::overflow_error& e) {
            std::cerr << "Overflow error in VNEG32 operation: " << e.what() << std::endl;
            //这里可以添加额外的错误处理逻辑，比如记录日志、设置错误标志等
            }
    res = (res_high << 32) | (res_low);
    
    write_Reg(176, vst, 1);
    write_Reg(dst_reg_id, res, 1);
    return res; 
}

inline uint64_t VIEU::do_VABS(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  
    if (bits_src2 == std::numeric_limits<int64_t>::min()) {
        res = bits_src2;  // 如果 Src = -2^63，直接赋值
    } else if (bits_src2 < 0) {
        res = -bits_src2;  // 如果 Src < 0 且 Src ≠ -2^63，取反
    } else {
        res = bits_src2;  // 如果 Src > 0，直接赋值
    }
    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 111_0100_000; execution cycle = 1

inline uint64_t VIEU::do_VABS32(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t res_low;
    int64_t res_high;
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  

    int32_t low_src2 = (bits_src2 ) & 0xFFFFFFFF;
    int32_t high_src2 = (bits_src2 >> 32) & 0xFFFFFFFF;

    if (low_src2 == std::numeric_limits<int64_t>::min()) {
        res_low = low_src2;  // 如果 Src = -2^63，直接赋值
    } else if (bits_src2 < 0) {
        res_low = -low_src2;  // 如果 Src < 0 且 Src ≠ -2^63，取反
    } else {
        res_low = low_src2;  // 如果 Src > 0，直接赋值
    }

    if (high_src2 == std::numeric_limits<int64_t>::min()) {
        res_high = high_src2;  // 如果 Src = -2^63，直接赋值
    } else if (bits_src2 < 0) {
        res_high = -high_src2;  // 如果 Src < 0 且 Src ≠ -2^63，取反
    } else {
        res_high = high_src2;  // 如果 Src > 0，直接赋值
    }

    uint64_t res = (res_high << 32) | res_low;
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 101_0100_000; execution cycle = 1

inline uint64_t VIEU::do_VMAX(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    int64_t bits_src1;
    std::memcpy(&bits_src1, &src1, sizeof(bits_src1));
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  
    if(bits_src1 > bits_src2){
        res = bits_src1;
    } else{res = bits_src1;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}//op = 111_0001_100; execution cycle = 1

inline uint64_t VIEU::do_VMAXU(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    
    if(src1 > src2){
        res = src1;
    } else{res = src2;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}//op = 110_0001_100; execution cycle = 1

inline uint64_t VIEU::do_VMAX32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src1 = src1 & 0xFFFFFFFF;
    int32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    if(low_src1 > low_src2){
        if(high_src1 > high_src2){res = (high_src1 << 32) | low_src1;}
        else{res = (high_src1 << 32) | low_src2;}
    }else{
        if(high_src1 > high_src2){res = (high_src2 << 32) | low_src1;}
        else{res = (high_src2 << 32) | low_src2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res; 
} //op = 101_0001_100; execution cycle = 1
    
inline uint64_t VIEU::do_VMAXU32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    if(low_src1 > low_src2){
        if(high_src1 > high_src2){res = (high_src1 << 32) | low_src1;}
        else{res = (high_src1 << 32) | low_src2;}
    }else{
        if(high_src1 > high_src2){res = (high_src2 << 32) | low_src1;}
        else{res = (high_src2 << 32) | low_src2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res; 
}//op = 100_0001_100; execution cycle = 1

inline uint64_t VIEU::do_VMIN(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    int64_t bits_src1;
    std::memcpy(&bits_src1, &src1, sizeof(bits_src1));
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  
    if(bits_src1 < bits_src2){
        res = bits_src1;
    } else{res = bits_src2;}
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0001_000; execution cycle = 1

inline uint64_t VIEU::do_VMINU(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    if(src1 < src2){
        res = src1;
    } else{res = src2;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}//op = 110_0001_000; execution cycle = 1

inline uint64_t VIEU::do_VMIN32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src1 = src1 & 0xFFFFFFFF;
    int32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    if(low_src1 > low_src2){
        if(high_src1 > high_src2){res = (static_cast<uint64_t>(high_src1) << 32) | low_src1;}
        else{res = (high_src1 << 32) | low_src2;}
    }else{
        if(high_src1 > high_src2){res = (static_cast<uint64_t>(high_src2) << 32) | low_src1;}
        else{res = (high_src2 << 32) | low_src2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res; 
} //op = 101_0001_000; execution cycle = 1

inline uint64_t VIEU::do_VMINU32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint32_t low_src1 = src1 & 0xFFFFFFFF; 
    uint32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint32_t low_src2 = src2 & 0xFFFFFFFF;
    uint32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    if(low_src1 < low_src2){
        if(high_src1 < high_src2){res = (high_src1 << 32) | low_src1;}
        else{res = (high_src1 << 32) | low_src2;}
    }else{
        if(high_src1 < high_src2){res = (high_src2 << 32) | low_src1;}
        else{res = (high_src2 << 32) | low_src2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res; 
} //op = 100_0001_000; execution cycle = 1

inline uint64_t VIEU::do_VEQ_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 
    if(src1 == src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0010_000; execution cycle = 1

inline uint64_t VIEU::do_VEQ_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 
    if(src1 == src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_1010_000; execution cycle = 1

inline uint64_t VIEU::do_VLT_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 
    int64_t bits_src1;
    std::memcpy(&bits_src1, &src1, sizeof(bits_src1));
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2)); 
    if(src1 < src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0010_010; execution cycle = 1
    
inline uint64_t VIEU::do_VLT_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    int64_t src1;
    std::memcpy(&src1, &imm, sizeof(src1));
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t src2;
    std::memcpy(&src2, &src2, sizeof(src2));
    double res; 
    if(src1 < src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 111_1010_010; execution cycle = 1
    
inline uint64_t VIEU::do_VLTU_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 

    if(src1 < src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}//op = 110_0010_010; execution cycle = 1
    
inline uint64_t VIEU::do_VLTU_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t res; 
    if(src1 < src2){
        res = 1;
    } else{res = 0;}
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 110_1010_010; execution cycle = 1

inline uint64_t VIEU::do_VEQ32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 == low_src2){
        if(high_src1 == high_src2){res = (mask1 << 32) | mask1;}
        else{res = ( mask2 << 32) | mask1;}
        if(high_src1 == high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | 0;}
    }else{
        if(high_src1 == high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 } //op = 101_0010_000; execution cycle = 1
    
inline uint64_t VIEU::do_VEQ32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = (static_cast<int64_t>(imm) << 58) >> 58;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 == low_src2){
        if(high_src1 == high_src2){res = (mask1 << 32) | mask1;}
        else{res = ( mask2 << 32) | mask1;}
        if(high_src1 == high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | 0;}
    }else{
        if(high_src1 == high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 }  //op = 101_1010_000; execution cycle = 1
    
inline uint64_t VIEU::do_VLT32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src1 = src1 & 0xFFFFFFFF;
    int32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 < low_src2){
        if(high_src1 < high_src2){res = (mask1 << 32) | mask1;}
        else{res = (mask2 << 32) | mask1;}
    }else{
        if(high_src1 < high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 }  //op = 101_0010_010; execution cycle = 1
    
inline uint64_t VIEU::do_VLT32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = (static_cast<int64_t>(imm) << 58) >> 58;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src1 = src1 & 0xFFFFFFFF;
    int32_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 < low_src2){
        if(high_src1 < high_src2){res = (mask1 << 32) | mask1;}
        else{res = (mask2 << 32) | mask1;}
    }else{
        if(high_src1 < high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 }

 inline uint64_t VIEU::do_VLTU32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 < low_src2){
        if(high_src1 < high_src2){res = (mask1 << 32) | mask1;}
        else{res = (mask2 << 32) | mask1;}
    }else{
        if(high_src1 < high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 } //op = 100_0010_010; execution cycle = 1
 inline uint64_t VIEU::do_VLTU32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){ 
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src1 = src1 & 0xFFFFFFFF;
    uint64_t high_src1 = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t mask1 = 1ULL;
    uint64_t mask2 = 0ULL;
    if(low_src1 < low_src2){
        if(high_src1 < high_src2){res = (mask1 << 32) | mask1;}
        else{res = (mask2 << 32) | mask1;}
    }else{
        if(high_src1 < high_src2){res = (mask1 << 32) | mask2;}
        else{res = (mask2 << 32) | mask2;}
    }

    write_Reg(dst_reg_id, res, 1);
    return res;
 }//op = 100_1010_010; execution cycle = 1

inline uint64_t VIEU::do_VMOV_VIEU(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    write_Reg(dst_reg_id, src2, 1);
    return src2;
} //op = 111_1110_001; execution cycle = 1
    
inline uint64_t VIEU::do_VMVCGC(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    int delay = 1;
    if(dst_reg_id == SVR0){ delay = 3;}
    write_Reg(dst_reg_id, src2, delay);
    return src2;
}
//op = 111_1110_010; execution cycle = 1/2
   
inline uint64_t VIEU::do_VMVCCG(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    int delay = 1;
    //to do：这里需要确定不同的delay；
    if(dst_reg_id == SVR0){ delay = 2;}
    write_Reg(dst_reg_id, src2, delay);
    return src2;
}

inline uint64_t VIEU::do_VMOVI_VIEU(uint64_t imm, int dst_reg_id){
    write_Reg(dst_reg_id, imm,1);
    return imm;
} //op 80位指令; execution cycle = 1

inline uint64_t VIEU::do_VMOVI24_VIEU(uint64_t imm, int dst_reg_id){
    uint64_t Imm = static_cast<int64_t>(imm << 40) >> 40;
    write_Reg(dst_reg_id, Imm,1);
    return Imm;
} 

inline uint64_t VIEU::do_VAND_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);  

    uint64_t res = src1 & src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0011_000; execution cycle = 1
    
inline uint64_t VIEU::do_VAND_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);  

    uint64_t res = src1 & src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_1011_000; execution cycle = 1
    
inline uint64_t VIEU::do_VOR_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res = src1 | src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0011_010; execution cycle = 1
    
inline uint64_t VIEU::do_VOR_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res = src1 | src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_1011_010; execution cycle = 1
   
inline uint64_t VIEU::do_VXOR_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res = src1 ^ src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0011_100; execution cycle = 1
    
inline uint64_t VIEU::do_VXOR_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res = src1 ^ src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 111_1011_100; execution cycle = 1
    
inline uint64_t VIEU::do_VNOT_src1_vr(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t res = ~ src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0011_110; execution cycle = 1
    
inline uint64_t VIEU::do_VNOT_src1_imm(uint64_t imm, int dst_reg_id){
    uint64_t src2 = imm;

    uint64_t res = ~ src2;

    write_Reg(dst_reg_id, res, 1);
    return res;
}  

inline uint64_t VIEU::do_VLZD(int src2_reg_id, int dst_reg_id){
    uint64_t src = read_Reg(src2_reg_id);

    uint64_t res = 0;
    if (src == 0) { res = 64;}  // 特殊情况：Src 为 0 时，前导 0 的个数为 64
    else{
        while ((src & (1ULL << 63)) == 0) {  // 检查最高位是否为 0
            src <<= 1;  // 左移 Src
            res++;
        }
    }
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 111_0101_100; execution cycle = 1
    
inline uint64_t VIEU::do_VLZD32(int src2_reg_id, int dst_reg_id){
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res_low = 0;
    if (low_src2 == 0) { res_low = 64;}  // 特殊情况：Src 为 0 时，前导 0 的个数为 64
    else{
        while ((low_src2 & (1ULL << 63)) == 0) {  // 检查最高位是否为 0
            low_src2 <<= 1;  // 左移 Src
            res_low++;
        }
    }
    uint64_t res_high = 0;
    if (high_src2 == 0) { res_high = 64;}  // 特殊情况：Src 为 0 时，前导 0 的个数为 64
    else{
        while ((high_src2 & (1ULL << 63)) == 0) {  // 检查最高位是否为 0
            high_src2 <<= 1;  // 左移 Src
            res_high++;
        }
    }

    uint64_t res = (res_high << 32) | res_low;
    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VSHFLL32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 << shift_num) | ((high_src2 << shift_num) << 32 );
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0000_0000_00; execution cycle = 1
    
inline uint64_t VIEU::do_VSHFLL32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res; 

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 << shift_num) | ((high_src2 << shift_num) << 32 );

    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VSHFLL_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int shift_num = src1 % 64;

    uint64_t res = src2 << shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0100_0000_00; execution cycle = 1
    

inline uint64_t VIEU::do_VSHFLL_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int shift_num = src1 % 64;
    res = src2 << shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VSHFLR32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 >> shift_num) | ((high_src2 >> shift_num) << 32 );

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0000_1000_00; execution cycle = 1
    
inline uint64_t VIEU::do_VSHFLR32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 >> shift_num) | ((high_src2 >> shift_num) << 32 );

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0010_1000_00; execution cycle = 1
  
inline uint64_t VIEU::do_VSHFLR_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int shift_num = src1 % 64;

    res = src2 >> shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0100_1000_00; execution cycle = 1
    
inline uint64_t VIEU::do_VSHFLR_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm; 
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int shift_num = src1 % 64;
    uint64_t res = src2 >> shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VSHFAR32_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 >> shift_num) | ((high_src2 >> shift_num) << 32 );

    write_Reg(dst_reg_id, res, 1);
    return res;
}//op = 0001_0000_00; execution cycle = 1

inline uint64_t VIEU::do_VSHFAR32_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = imm;
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    int32_t low_src2 = src2 & 0xFFFFFFFF;
    int32_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    int shift_num = src1 % 32;

    res = (low_src2 >> shift_num) | ((high_src2 >> shift_num) << 32 );

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0011_0000_00; execution cycle = 1

inline uint64_t VIEU::do_VSHFAR_src1_vr(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  

    int shift_num = src1 % 64;

    res = bits_src2 >> shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0101_0000_00; execution cycle = 1

inline uint64_t VIEU::do_VSHFAR_src1_imm(uint64_t imm, int src2_reg_id, int dst_reg_id){
    uint64_t Src1 = static_cast<uint64_t>(imm);
    uint64_t src2 = read_Reg(src2_reg_id);
    int64_t res;
    int64_t bits_src2;
    std::memcpy(&bits_src2, &src2, sizeof(bits_src2));  

    int shift_num = Src1 % 64;
    res = bits_src2 >> shift_num;
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 0111_0000_00; execution cycle = 1


inline uint64_t VIEU::do_VBCLR32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t res;
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint32_t low_src2 = static_cast<uint32_t>(src2 & 0xFFFFFFFF);
    uint32_t high_src2 = static_cast<uint32_t>((src2 >> 32) & 0xFFFFFFFF);

    if (src1 > 31) {
        res = src2;  // 如果位置超出 31 位，保持原数据输出
    } else {
        // 清零指定位置
        res = ((high_src2 & ~(1ULL << src1)) << 32 ) | (low_src2 & ~(1ULL << src1));  // 使用按位与和按位取反操作清零第 Src1 位
    }
     
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0000_0010_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBCLR(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
 
    uint64_t res = src2 & ~(1ULL << src1);  // 使用按位与和按位取反操作清零第 Src1 位
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VBSET32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;


    uint32_t low_src2 = static_cast<uint32_t>(src2 & 0xFFFFFFFF);
    uint32_t high_src2 = static_cast<uint32_t>((src2 >> 32) & 0xFFFFFFFF);

    if (src1 > 31) {
        res = src2;  // 如果位置超出 31 位，保持原数据输出
    } else {
        // 清零指定位置
        res = ((high_src2 | (1ULL << src1)) << 32 ) | (low_src2 | (1ULL << src1));  // 使用按位与和按位取反操作清零第 Src1 位
    }
     
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0000_1010_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBSET(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
  
    uint64_t res = src2 | (1ULL << src1);  // 使用按位与和按位取反操作清零第 Src1 位

    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 0100_1010_00; execution cycle = 1

inline uint64_t VIEU::do_VBEX32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint32_t low_src2 = static_cast<uint32_t>(src2 & 0xFFFFFFFF);
    uint32_t high_src2 = static_cast<uint32_t>((src2 >> 32) & 0xFFFFFFFF);

    if (src1 > 31) {
        res = src2;  // 如果位置超出 31 位，保持原数据输出
    } else {
        // 清零指定位置
        res = ((high_src2 ^ (1ULL << src1)) << 32 ) | (low_src2 ^ (1ULL << src1));  
    }
     
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 0001_0010_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBEX(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res = src2 ^ (1ULL << src1);  

    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0101_0010_00; execution cycle = 1

inline uint64_t VIEU::do_VBTST32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;

    uint64_t low_src2 = src2 & 0xFFFFFFFF;
    uint64_t high_src2 = (src2 >> 32) & 0xFFFFFFFF;
    if (src1 > 31) {
        // 如果测试位超出 63，保持原数据输出
        res = src2;
    } else {
        // 生成测试掩码
        uint32_t mask = 1ULL << src1;

        // 测试 Src2 的第 Src1 位
        if ((low_src2 & mask) == 0) {
            // 如果测试位为 0，设置 Dst 的对应位为 1
            low_src2 |= mask;
        } else {
            // 如果测试位为 1，保持 Dst 的对应位为 0
            low_src2 &= ~mask;
        }
        if ((high_src2 & mask) == 0) {
            // 如果测试位为 0，设置 Dst 的对应位为 1
            high_src2 |= mask;
        } else {
            // 如果测试位为 1，保持 Dst 的对应位为 0
            high_src2 &= ~mask;
        }
    }
    res = (high_src2 << 32 ) | low_src2;
     
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 0001_1010_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBTST(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    uint64_t res;
    if (src1 > 31) {
        // 如果测试位超出 63，保持原数据输出
        res = src2;
    } else {
        // 生成测试掩码
        uint32_t mask = 1ULL << src1;

        // 测试 Src2 的第 Src1 位
        if ((src2 & mask) == 0) {
            // 如果测试位为 0，设置 Dst 的对应位为 1
            src2 |= mask;
        } else {
            // 如果测试位为 1，保持 Dst 的对应位为 0
            src2 &= ~mask;
        }
        res = src2;
    }
    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VBEXT32(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t Src1  = read_Reg(src1_reg_id);
    uint64_t Src2  = read_Reg(src2_reg_id);
    int64_t src1;
    std::memcpy(&src1, &Src1,sizeof(src1));
    int64_t src2;
    std::memcpy(&src2, &Src2,sizeof(src2));
    // 提取 csta 和 cstb
    uint32_t csta = (src1 >> 6) & 0x3F;
    uint32_t cstb = src1 & 0x3F;

    uint64_t res;
    int64_t res_low = (src1) & 0xFFFFFFFF;
    int64_t res_high = (src1 >> 32) & 0xFFFFFFFF;
    // 检查 csta 和 cstb 是否有效
    if (csta >= 32 || cstb >= 32) {
        res = Src2;  // 结果保持原数据输出
        // 置位 oversize 位（假设 oversize 位是 dst 的最高位）
    } else {
        // 根据 csta 和 cstb 的关系截取数据
        if (cstb >= csta) {
            // 截取数据位段为 {31-csta, cstb-csta}
            int32_t mask = (1 << (cstb - csta + 1)) - 1;
            res_high = (src2 >> (31 - csta)) & mask;
            res_low = (src2 >> (31 - csta)) & mask;
            // 将截取位段右移 cstb-csta 位，高位补充 cstb 个符号位
            int64_t sign_bit_high = res_high >> (cstb - csta);
            int64_t sign_bit_low = res_low >> (cstb - csta);
            res_high = (res_high << (32 - (cstb - csta))) | (sign_bit_high << (32 - (cstb - csta) - 1));
            res_low = (res_low << (32 - (cstb - csta))) | (sign_bit_low << (32 - (cstb - csta) - 1));
        } else {
            // 截取数据位段为 {31-csta, 0}
            int64_t res_high = (src2 >> (31 - csta)) & 0xFFFFFFFF;
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
            int64_t sign_bit_high = res_high >> (31 - csta);
            res_high = (res_high << (csta - cstb)) | (sign_bit_high << (32 - (csta - cstb) - 1));
            int64_t res_low = (src2 >> (31 - csta)) & 0xFFFFFFFF;
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
            int64_t sign_bit_low = res_high >> (31 - csta);
            res_low = (res_low << (csta - cstb)) | (sign_bit_low << (32 - (csta - cstb) - 1));
        }
        // 将截取的数据扩展为 32 位有符号整数
        res = (res_high << 32) | res_low;
    }
    write_Reg(dst_reg_id, res, 1);
    return res;
} //op = 0010_0010_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBEXT(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t Src1  = read_Reg(src1_reg_id);
    uint64_t Src2  = read_Reg(src2_reg_id);
    int64_t src1;
    std::memcpy(&src1, &Src1,sizeof(src1));
    int64_t src2;
    std::memcpy(&src2, &Src2,sizeof(src2));
    // 提取 csta 和 cstb
    uint32_t csta = (src1 >> 6) & 0x3F;
    uint32_t cstb = src1 & 0x3F;

    uint64_t res;

    int64_t mask = (1ULL << (cstb - csta + 1)) - 1;
    res = (src2 >> (63 - csta)) & mask;

    if (cstb >= csta) {
            // 将截取位段右移 cstb-csta 位，高位补充 cstb 个符号位
        int64_t sign_bit = res & (1ULL << (cstb - csta));
        res = (sign_bit ? -1ULL : 0) << (63 - cstb) | (res >> (cstb - csta));
    } else {
            // 截取数据位段为 {63-csta, 0}
        int64_t res = (src2 >> (63 - csta));
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
        int64_t sign_bit = res & (1ULL << (csta - cstb));
        res = (sign_bit ? -1ULL : 0) << (63 - cstb) | (res << (csta - cstb));
    }
        // 将截取的数据扩展为 32 位有符号整数

    write_Reg(dst_reg_id, res, 1);
    return res;
}

inline uint64_t VIEU::do_VBEXT32U(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1  = read_Reg(src1_reg_id);
    uint64_t src2  = read_Reg(src2_reg_id);

    // 提取 csta 和 cstb
    uint32_t csta = (src1 >> 6) & 0x3F;
    uint32_t cstb = src1 & 0x3F;

    uint64_t res;
    uint64_t res_low = (src1) & 0xFFFFFFFF;
    uint64_t res_high = (src1 >> 32 ) & 0xFFFFFFFF;
    // 检查 csta 和 cstb 是否有效
    if (csta >= 32 || cstb >= 32) {
        res = src2;  // 结果保持原数据输出
        // 置位 oversize 位（假设 oversize 位是 dst 的最高位）
    } else {
        // 根据 csta 和 cstb 的关系截取数据
        if (cstb >= csta) {
            // 截取数据位段为 {31-csta, cstb-csta}
            uint32_t mask = (1 << (cstb - csta + 1)) - 1;
            res_high = (src2 >> (31 - csta)) & mask;
            res_low = (src2 >> (31 - csta)) & mask;
            // 将截取位段右移 cstb-csta 位，高位补充 cstb 个符号位
            uint64_t sign_bit_high = res_high >> (cstb - csta);
            uint64_t sign_bit_low = res_low >> (cstb - csta);
            res_high = (res_high << (32 - (cstb - csta))) | (sign_bit_high << (32 - (cstb - csta) - 1));
            res_low = (res_low << (32 - (cstb - csta))) | (sign_bit_low << (32 - (cstb - csta) - 1));
        } else {
            // 截取数据位段为 {31-csta, 0}
            uint64_t res_high = (src2 >> (31 - csta)) & 0xFFFFFFFF;
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
            uint64_t sign_bit_high = res_high >> (31 - csta);
            res_high = (res_high << (csta - cstb)) | (sign_bit_high << (32 - (csta - cstb) - 1));
            uint64_t res_low = (src2 >> (31 - csta)) & 0xFFFFFFFF;
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
            uint64_t sign_bit_low = res_high >> (31 - csta);
            res_low = (res_low << (csta - cstb)) | (sign_bit_low << (32 - (csta - cstb) - 1));
        }
        // 将截取的数据扩展为 32 位有符号整数
        res = (res_high << 32) | res_low;
    }
    write_Reg(dst_reg_id, res, 1);
    return res;
}  //op = 0010_1010_00; execution cycle = 1
   
inline uint64_t VIEU::do_VBEXTU(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1  = read_Reg(src1_reg_id);
    uint64_t src2  = read_Reg(src2_reg_id);
    // 提取 csta 和 cstb
    uint32_t csta = (src1 >> 6) & 0x3F;
    uint32_t cstb = src1 & 0x3F;

    uint64_t res;
    
    int64_t mask = (1ULL << (cstb - csta + 1)) - 1;
    res = (src2 >> (63 - csta)) & mask;

    if (cstb >= csta) {
            // 将截取位段右移 cstb-csta 位，高位补充 cstb 个符号位
        uint64_t sign_bit = res & (1ULL << (cstb - csta));
        res = (sign_bit ? -1ULL : 0) << (63 - cstb) | (res >> (cstb - csta));
    } else {
            // 截取数据位段为 {63-csta, 0}
        uint64_t res = (src2 >> (63 - csta));
            // 将所截取的位段左移 csta-cstb 位，高位补充 cstb 个符号位
        uint64_t sign_bit = res & (1ULL << (csta - cstb));
        res = (sign_bit ? -1ULL : 0) << (63 - cstb) | (res << (csta - cstb));
        }
        // 将截取的数据扩展为 32 位有符号整数

    write_Reg(dst_reg_id, res, 1);
    return res;
} 

inline uint64_t VIEU::do_VBALE2(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    
    uint64_t src1_low = src1 & 0xFFFFFFFF;
    uint64_t src2_low = src2 & 0xFFFFFFFF;

    uint64_t res = (src2_low << 32 ) | src1_low;

    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 0000_0100_00; execution cycle = 1
    
inline uint64_t VIEU::do_VBALE2H(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t src1_high = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t src2_high = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res = (src2_high << 32 ) | src1_high;

    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 0000_1100_00; execution cycle = 1
  
inline uint64_t VIEU::do_VBALE2LH(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t src1_low = src1 & 0xFFFFFFFF;
    uint64_t src2_high = (src2 >> 32) & 0xFFFFFFFF;

    uint64_t res = (src2_high << 32 ) | src1_low;

    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 0001_0100_00; execution cycle = 1
  
inline uint64_t VIEU::do_VBALE2HL(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t src1_high = (src1 >> 32) & 0xFFFFFFFF;
    uint64_t src2_low = src2 & 0xFFFFFFFF;

    uint64_t res = (src2_low << 32 ) | src1_high;

    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 0001_1100_00; execution cycle = 1
  
inline uint64_t VIEU::do_VBALE4H(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);

    uint64_t src1_low_high= (src1 >> 16) & 0xFFFF;
    uint64_t src1_high_high= (src1 >> 48) & 0xFFFF;
    uint64_t src2_low_high= (src2 >> 16) & 0xFFFF;
    uint64_t src2_high_high= (src2 >> 48) & 0xFFFF;

    uint64_t res = (src2_high_high << 48 ) | (src2_low_high << 32) | (src1_high_high << 16) | src1_low_high;

    write_Reg(dst_reg_id,res,1);
    return res;
}//op = 0010_0100_00; execution cycle = 1
  
inline uint64_t VIEU::do_VBALE4L(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    
    uint64_t src1_low_low= src1 & 0xFFFF;
    uint64_t src1_high_low= (src1 >> 32) & 0xFFFF;
    uint64_t src2_low_low= src2 & 0xFFFF;
    uint64_t src2_high_low= (src2 >> 32) & 0xFFFF;

    uint64_t res = (src2_high_low << 48 ) | (src2_low_low << 32) | (src1_high_low << 16) | src1_low_low;

    write_Reg(dst_reg_id,res,1);
    return res;
}

inline uint64_t VIEU::do_VSBALE2(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    
    int64_t bits_src1;
    std::memcpy(&bits_src1,&src1,sizeof(bits_src1));
    int64_t src1_low = bits_src1 & 0xFFFFFFFF;
    int64_t bits_src2;
    std::memcpy(&bits_src2,&src2,sizeof(bits_src2));
    int64_t src2_low = bits_src2 & 0xFFFFFFFF;
    if(bits_src1 > 0x7FFFFFFF){src1_low = 0x7FFFFFFF;}
    else if(bits_src1 < 0x80000000){src1_low = 0x80000000;}
    if(bits_src2 > 0x7FFFFFFF){src2_low = 0x7FFFFFFF;}
    else if(bits_src2 < 0x80000000){src2_low = 0x80000000;}
    uint64_t res = (src2_low << 32 ) | src1_low;

    write_Reg(dst_reg_id,res,1);
    return res;
}  //op = 0011_0100_00; execution cycle = 1
    
inline uint64_t VIEU::do_VSBALE4(int src1_reg_id, int src2_reg_id, int dst_reg_id){
    uint64_t src1 = read_Reg(src1_reg_id);
    uint64_t src2 = read_Reg(src2_reg_id);
    
    int64_t src1_low = src1 & 0xFFFFFFFF;
    int64_t src1_high = (src1 >> 32) & 0xFFFFFFFF;
    int64_t src1_low_low= src1 & 0xFFFF;
    int64_t src1_high_low= (src1 >> 32) & 0xFFFF;
    if(src1_low > 0xFFFF){src1_low_low = 0xFFFF;}
    else if(src1_low < 0x0000){src1_low_low = 0x0000;}
    if(src1_high > 0xFFFF){src1_high_low = 0xFFFF;}
    else if(src1_high < 0x0000){src1_high_low = 0x0000;}

    int64_t src2_low = src2 & 0xFFFFFFFF;
    int64_t src2_high = (src2 >> 32) & 0xFFFFFFFF;
    int64_t src2_low_low= src2  & 0xFFFF;
    int64_t src2_high_low= (src2 >> 48) & 0xFFFF;
    if(src2_low > 0xFFFF){src2_low_low = 0xFFFF;}
    else if(src2_low < 0x0000){src2_low_low = 0x0000;}
    if(src2_high > 0xFFFF){src2_high_low = 0xFFFF;}
    else if(src2_high < 0x0000){src2_high_low = 0x0000;}

    uint64_t res = (src2_high_low << 48 ) | (src2_low_low << 32) | (src1_high_low << 16) | src1_low_low;

    write_Reg(dst_reg_id,res,1);
    return res;
} //op = 0011_1100_00; execution cycle = 1
    
inline uint64_t VIEU::do_VUBALE4H(int src2_reg_id, int dst_reg_id){
    uint64_t src = read_Reg(src2_reg_id);
    
    uint64_t src_low_high= (src >> 16) & 0xFFFF;
    uint64_t src_high_high= (src >> 48) & 0xFFFF;

    uint64_t res = (src_high_high << 32) | src_low_high;

} //op = 0100_0100_00; execution cycle = 1
    
inline uint64_t VIEU::do_VUBALE4L(int src2_reg_id, int dst_reg_id){
    uint64_t src = read_Reg(src2_reg_id);

    uint64_t src_low_low= src & 0xFFFF;
    uint64_t src_high_low= (src >> 32) & 0xFFFF;

    uint64_t res = (src_high_low << 32) | src_low_low;

} //op = 0100_1100_00; execution cycle = 1

inline uint64_t VIEU::do_VITL2(int src2_reg_id, int dst_reg_id){
    uint64_t src = read_Reg(src2_reg_id);

    uint64_t src_low= src & 0xFFFFFFFF;
    uint64_t src_high= (src >> 32) & 0xFFFFFFFF;

    uint64_t res = (src_low << 32) | src_high;
} //op = 0101_0100_00; execution cycle = 1
    
inline uint64_t VIEU::do_VITL4(int src2_reg_id, int dst_reg_id){
    uint64_t src = read_Reg(src2_reg_id);

    uint64_t src_low_low= src & 0xFFFF;
    uint64_t src_low_high= (src >> 16) & 0xFFFF;
    uint64_t src_high_low= (src >> 32) & 0xFFFF;
    uint64_t src_high_high= (src >> 48) & 0xFFFF;

    uint64_t res = (src_high_low << 48 ) | (src_high_high << 32) | (src_low_low << 16) | src_low_high;

} //op = 0101_1100_00; execution cycle = 1

uint64_t VIEU::Execute(instruction* vieu_instr){
    //do_VADDU_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(), )
    switch (vieu_instr->get_opcode()){
    case VADD_src1_vr:
        return do_VADD_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADD_src1_imm:
        return do_VADD_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADDU_src1_vr:
        return do_VADDU_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADDU_src1_imm:
        return do_VADDU_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());

    case VADD32_src1_vr:
        return do_VADD32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADD32_src1_imm:
        return do_VADD32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADDU32_src1_vr:
        return do_VADDU32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VADDU32_src1_imm:
        return do_VADDU32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUB_src1_vr:
        return do_VSUB_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUB_src1_imm:
        return do_VSUB_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUBU_src1_vr:
        return do_VSUBU_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUBU_src1_imm:
        return do_VSUBU_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUBC:
        return do_VSUBC(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VSUB32_src1_vr:
        return do_VSUB32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUB32_src1_imm:
        return do_VSUB32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VSUBU32_src1_vr:
        return do_VSUBU32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSUBU32_src1_imm:
        return do_VSUBU32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VSUBC32:
        return do_VSUBC32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSAT:
        return do_VSAT(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSAT32:
        return do_VSAT32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VNEG:
        return do_VNEG(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VNEG32:
        return do_VNEG32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VABS:
        return do_VABS(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VABS32:
        return do_VABS32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VMAX:
        return do_VMAX(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VMAX32:
        return do_VMAX32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VMAXU:
        return do_VMAXU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VMAXU32:
        return do_VMAXU32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());  
    case VMIN:
        return do_VMIN(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VMIN32:
        return do_VMIN32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VMINU:
        return do_VMINU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VMINU32:
        return do_VMINU32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());                                    
    case VEQ_src1_vr:
        return do_VEQ_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VEQ_src1_imm:
        return do_VEQ_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLT_src1_vr:
        return do_VLT_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLT_src1_imm:
        return do_VLT_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLTU_src1_vr:
        return do_VLTU_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLTU_src1_imm:
        return do_VLTU_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VEQ32_src1_vr:
        return do_VEQ32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VEQ32_src1_imm:
        return do_VEQ32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLT32_src1_vr:
        return do_VLT32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLT32_src1_imm:
        return do_VLT32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLTU32_src1_vr:
        return do_VLTU32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VLTU32_src1_imm:
        return do_VLTU32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
 
    case VMOV_VIEU:
        return do_VMOV_VIEU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VMVCGC:
        return do_VMVCGC(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VMVCCG:
        return do_VMVCCG(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VMOVI_VIEU:
        return do_VMOVI_VIEU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VMOVI24_VIEU:
        return do_VMOVI24_VIEU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VAND_src1_vr:
        return do_VAND_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VAND_src1_imm:
        return do_VAND_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VOR_src1_vr:
        return do_VOR_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VOR_src1_imm:
        return do_VOR_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VXOR_src1_vr:
        return do_VXOR_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VXOR_src1_imm:
        return do_VXOR_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VNOT_src1_vr:
        return do_VNOT_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VNOT_src1_imm:
        return do_VNOT_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VLZD:
        return do_VLZD(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VLZD32:
        return do_VLZD32(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VSHFLL_src1_vr:
        return do_VSHFLL_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFLL_src1_imm:
        return do_VSHFLL_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());

    case VSHFLL32_src1_vr:
        return do_VSHFLL32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFLL32_src1_imm:
        return do_VSHFLL32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFLR_src1_vr:
        return do_VSHFLR_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFLR_src1_imm:
        return do_VSHFLR_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());

    case VSHFLR32_src1_vr:
        return do_VSHFLR32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFLR32_src1_imm:
        return do_VSHFLR32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFAR_src1_vr:
        return do_VSHFAR_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFAR_src1_imm:
        return do_VSHFAR_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());

    case VSHFAR32_src1_vr:
        return do_VSHFAR32_src1_vr(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSHFAR32_src1_imm:
        return do_VSHFAR32_src1_imm(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBCLR:
        return do_VBCLR(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBCLR32:
        return do_VBCLR32(static_cast<immediate_operand*>(vieu_instr->get_operands(0))->get_imme_value(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBSET:
        return do_VBSET(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBSET32:
        return do_VBSET32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEX:
        return do_VBEX(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEX32:
        return do_VBEX32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBTST:
        return do_VBTST(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBTST32:
        return do_VBTST32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEXT:
        return do_VBEXT(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEXT32:
        return do_VBEXT32(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEXTU:
        return do_VBEXTU(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBEXT32U:
        return do_VBEXT32U(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE2:
        return do_VBALE2(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE2H:
        return do_VBALE2H(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE2LH:
        return do_VBALE2LH(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE2HL:
        return do_VBALE2HL(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE4H:
        return do_VBALE4H(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VBALE4L:
        return do_VBALE4L(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSBALE2:
        return do_VSBALE2(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VSBALE4:
        return do_VSBALE4(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id(),
                                        static_cast<register_operand*>(vieu_instr->get_operands(2))->get_reg_id());
    case VUBALE4H:
        return do_VUBALE4H(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VUBALE4L:
        return do_VUBALE4L(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VITL2:
        return do_VITL2(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());
    case VITL4:
        return do_VITL4(static_cast<register_operand*>(vieu_instr->get_operands(0))->get_reg_id(),
                                    static_cast<register_operand*>(vieu_instr->get_operands(1))->get_reg_id());

    }
};